
library ieee;

use IEEE.STD_LOGIC_1164.ALL;

 -- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
 --library UNISIM;
--use UNISIM.VComponents.all;

entity adder is
 generic(n: INTEGER := 32);
 Port ( 
 input1, input2 : in STD_LOGIC_VECTOR (n-1 downto 0);
 output : out STD_LOGIC_VECTOR (n-1 downto 0)

 );
end adder;

architecture Behavioral of adder is

component FullAdder
 Port ( x : in STD_LOGIC;
 y : in STD_LOGIC;
 z : in STD_LOGIC;
 s : out STD_LOGIC;
 c : out STD_LOGIC);
end component;

signal t: std_logic_vector(n downto 0);
signal in1,in2,outp: std_logic_vector(n-1 downto 0);


begin

 t(0) <= '0';
 in1<=input1;
 in2<=input2;

 FA: for i in 0 to n-1 generate
 FA_i: FullAdder PORT MAP (t(i), in1(i), in2(i), outp(i), t(i+1));

 end generate;

 output<=outp;

end Behavioral;